2023 update: x86-64 CPUs now support 57-bit virtual address-space (with an extra level of page-tables, PML5, so OSes may not enable it when not needed to avoid making page walks slower on TLB miss.) This gives the OS room to map all that physical address-space as CPUs have continued to support bigger DIMMs in their memory controllers, and more bits of physical address-space to go with it in their cache tags and TLBs, and internal buses that transmit physical addresses of cache line.