With SteadyClock FS the focus was put on reducing the self jitter of SteadyClock to new lows, by improving its second, analog PLL circuit, and referencing both Direct Digital Synthesis and PLL to a low phase noise quartz crystal. The self jitter measured through DA conversion now reaches levels that usually are only available in master quartz clock mode, while SteadyClock still always runs in PLL mode - no matter if internal or external clock, sound is exactly the same (again). The low phase noise oscillator driving the updated circuit reaches jitter specs lower than a picosecond (ps), an area called FemtoSecond. Hence SteadyClock FS.