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AMD designed the CPU with more robust x86 instruction decoding capabilities than that of K6, to enhance its ability to keep more data in-flight at once.[28] The critical branch-predictor unit was enhanced compared to the K6. Deeper pipelining with more stages allowed higher clock speeds to be attained.[31] Like the AMD K5 and K6, the Athlon dynamically buffered internal micro-instructions at runtime resulting from parallel x86 instruction decoding. The CPU is an out-of-order design, again like previous post-5x86 AMD CPUs. The Athlon utilizes the Alpha 21264's EV6 bus architecture with double data rate (DDR) technology.[citation needed]